1. Field of the Invention
The invention relates to a method of verifying a design of a logic circuit, and specifically, relates to a verification of a function or an operation of the semiconductor device at power-off/on.
2. Description of the Related Art
It is essential to design a semiconductor circuit (herein after called an LSI) having low power consumption in order to use it in cellular phones. To satisfy this requirement, several ways to perform the low power consumption have been presented. One of them is that the power line for a certain circuit block, whose function is halted in response to a state of the operation mode, is physically disconnected.
In development of the LSI, when a design for a particular circuit is made, a function or an operation of the circuit designed in the logic level is verified by computer simulation. When an LSI having a function that un-used circuit block is electrically disconnected is designed, the entire circuit of the LSI is divided into circuit blocks for simulation, each of which uses a same power supply, in order to verify the function of the entire circuit. Then, the function of each circuit block is verified by comparing with verification patterns for each divided circuit block.
Thus, when the simulation is performed for each circuit block, it is required to generate a verification pattern for each circuit block to be compared. Thus, it is required to spend time and human effort to prepare the simulation, perform the simulation, and analyze the results of the simulation. In some cases, some circuits, which should not be divided, may be divided by accident during the circuit dividing process. To resolve this problem, it has been proposed to insert a pseudo-cell between the circuit blocks, each of which is operated with a different power supply so that a logic level of a signal applied to a circuit block at the next stage can be controlled. As a result, the function of the entire circuit is verified.
FIG. 2 is a diagram for a circuit subjected to simulation, in which a pseudo-cell is placed between circuit blocks: The circuit 100, which is subjected simulation, includes a first circuit block A operated by supplying a first supply voltage VddA, and a second circuit block B operated by supplying a second supply voltage VddB. The first circuit block A outputs a first output signal SA in response to first and second signals IN1 and IN2, and the second circuit block B outputs a second output signal SB in response to the first output signal SA from the first circuit block A, and third and fourth signals IN3 and IN4. The first output signal SA, outputted from the first circuit block A, is supplied to the second circuit block B through a first pseudo-cell B101 having a control terminal connected to the first supply voltage VddA. The second output signal SB, outputted from the second circuit block B, is outputted as an output signal OUT through a second pseudo-cell B102 having a control terminal connected to the second supply voltage VddB. In the circuit 100, a three-state buffer is used for each of the first and second pseudo-cells B101 and B102. The three-state buffer used in the first pseudo-cell B101 outputs a signal having a logic level that is the same as the first output signal SA, when the first power supply VddA having the logic level “1” is applied to its control terminal, and causes its output terminal to reach a high impedance state when the first power supply VddA having the logic level “0” is applied to its control terminal. Similarly, the three-state buffer used in the second pseudo-cell B102 outputs a signal having a logic level that is the same as the second output signal SB, when the second power supply VddB having the logic level “1” is applied to its control terminal, and causes its output terminal to reach a high impedance state when the second power supply VddB having the logic level “0” is applied to its control terminal.
When the simulation is performed with the circuit 100 shown in FIG. 2, there is an advantage that the function of the entire circuit can be verified for its function. On the other hand, if one of the circuit blocks A and B includes a storage element, such as a flip-flop circuit, a certain signal level is maintained in the circuit block, whose power supply should be disconnected for the purpose of verification. For this reason, since the verification using the circuit 100 after reconnecting the power supply is not followed to the real circuit, the verification by this method is not completed to verify all of the circuits of the LSI.
To overcome this problem, another simulation method has been presented, as shown in JP 2002-259487. The simulation disclosed in JP 2002-259487 is a multiple-power-supply circuit simulation. In this simulation, a pseudo power supply cell having an input terminal is disposed in each of a plurality of functional hierarchies of circuit data in a circuit subjected to a simulation. Execution circuit data connecting each power supply terminal of the functional hierarchies and each input terminal of the arranged pseudo power supply cell, respectively, are created and read. A change in input-signal level is detected in accordance with a verification signal pattern. In response to the level of the input terminal of the pseudo power supply cell at the time of the input signal level change, a judgment is made as to whether or not the power supply of the hierarchies subjected turns on or off. A simulation for only the subjected hierarchy whose power supply is turned on is performed. As a result, it is possible easily to perform the simulation at the time of the connection with or disconnection from power supply for the multiple power supply circuit, so that an increase in the number of verification steps can be suppressed, and the duration of verification can be shortened.
However, according to the simulation disclosed in JP 2002-259487, it is difficult to detect the misconnection of the logic cells in each functional hierarchy, and also difficult to verify whether or not all data stored in the circuit is clear. Further, since the simulation disclosed in JP 2002-259487 is quit different from the conventional simulation described above, a conventional simulator cannot be used for it.